Semiconductor memory devices can typically be classified on the basis of memory functionality, data access patterns and the nature of the data storage mechanism. For example, distinctions are typically made between read-only memory (ROM) devices and read-write memory (RWM) devices. The RWM devices typically have the advantage of offering both read and write functionality with comparable data access times. Typically, in RWM devices, data can be stored in flip-flops for “static” memory devices or as preset levels of charge on a capacitor in “dynamic” memory devices. As will be understood by those skilled in the art, static memory devices retain their data as long as a supply of power is maintained, however, dynamic memory devices require periodic data refreshing to compensate for potential charge leakage. Because RWM devices use active circuitry to store data, they belong to a class of memory devices known as “volatile” memory devices because data stored therein will be lost upon termination of the power supply. ROM devices, on the other hand, may encode data into circuit topology (e.g., by blowing fuses, removing diodes, etc.). Because this latter type of data storage may be hardwired, the data cannot be modified, but can only be read. ROM devices also typically belong to a class of memory devices known as “nonvolatile” memory devices because data stored therein will typically not be lost upon termination of the power supply. Other types of memory devices include nonvolatile read-write (NVRWM) memory devices. These types of nonvolatile memory devices may operate as erasable programmable read-only memory (EPROM) devices, electrically erasable programmable read-only memory (E2PROM) devices and flash memory devices, for example.
An additional memory classification is typically based on the order in which data can be accessed. Here, most memory devices belong to the random-access class, which means that memory locations can be read from or written to in random order. Notwithstanding the fact that most memory devices provide random-access, typically only random-access RWM memories use the acronym RAM. Alternatively, memory devices may restrict the order of data access to achieve shorter data access times, reduce layout area and/or provide specialized functionality. Examples of such specialized memory devices include buffer memory devices such as first-in first-out (FIFO) memory devices, last-in first-out (LIFO or “stack”) memory devices, shift registers and content-addressable memory (CAM) devices.
A final classification of semiconductor memories is based on the number of data input and data output ports associated with the memory cells therein. For example, although most memory devices have unit cells therein that provide only a single port, which is shared to provide an input and output path for transfer of data, memory devices with higher bandwidth requirements often have cells therein with multiple input and output ports. However, the addition of ports to unit memory cells typically increases the complexity and layout area requirements for these higher bandwidth memory devices.
Single-port memory devices are typically made using static RAM cells if fast data access times are a requirement, and dynamic RAM cells if low cost is a primary requirement. Many FIFO memory devices use dual-port RAM based designs with self-incrementing internal read and write pointers to achieve fast fall-through capability. As will be understood by those skilled in the art, fall-through capability is typically measured as the time elapsing between the end of a write cycle into a previously empty FIFO and the time an operation to read that data may begin. Exemplary FIFO memory devices are more fully described and illustrated at section 2.2.7 of a textbook by A. K. Sharma entitled “Semiconductor Memories: Technology, Testing and Reliability”, IEEE Press (1997).
In particular, dual-port SRAM-based FIFOs typically utilize separate read and write pointers to advantageously allow read and write operations to occur independently of each other and achieve fast fall-through capability as data written into a dual-port SRAM FIFO can be immediately accessed for reading. Since these read and write operations may occur independently, independent read and write clocks having different frequencies may be provided to enable the FIFO to act as a buffer between peripheral devices operating at different rates. Unfortunately, a major disadvantage of typical dual-port SRAM-based FIFOs is the relatively large unit cell size for each dual-port SRAM cell therein. Thus, for a given semiconductor chip size, dual-port buffer memory devices typically provide less memory capacity relative to single-port buffer memory devices. For example, using a standard DRAM cell as a reference unit cell consuming one (1) unit of area, a single-port SRAM unit cell typically may consume four (4) units of area and a dual-port SRAM unit cell typically may consume sixteen (16) units of area. Moreover, the relatively large unit cells of a dual-port SRAM FIFO limit the degree to which the number of write operations can exceed the number of read operations before the FIFO becomes full.
To address these limitations of dual-port buffer memory devices, single-port buffer memory devices have been developed to, among other things, achieve higher data capacities for a given semiconductor chip size. For example, U.S. Pat. No. 5,546,347 to Ko et al. entitled “Interleaving Architecture And Method For A High Density FIFO”, assigned to the present assignee, discloses a memory device that has high capacity and uses relatively small single-port memory cells. However, the use of only single port memory cells typically precludes simultaneous read and write access to data in the same memory cell, which means that single-port buffer memory devices typically have slower fall-through time than comparable dual-port memory devices. Moreover, single-port buffer memory devices may use complicated arbitration hardware to control sequencing and queuing of reading and writing operations.
U.S. Pat. No. 5,371,708 to Kobayashi also discloses a FIFO memory device containing a single-port memory array, a read data register for holding read data from the memory array and a write data register for holding data to be written into the memory array. A bypass switch is also provided for transferring data from the write data register to the read data register so that the memory array can be bypassed during testing of the FIFO to detect the presence of defects therein. However, like the above-described single-port buffer memory devices, simultaneous read and write access to data is not feasible.
Commonly assigned U.S. Pat. Nos. 5,978,307, 5,982,700 and 5,998,478 disclose FIFO memory devices having generally fast fall-through capability. These memory buffers contain a tri-port memory array of moderate capacity having nonlinear columns of tri-port cells therein, which collectively form four separate registers, and a substantially larger capacity supplemental memory array (e.g., DRAM array) having cells therein with reduced unit cell size. The tri-port memory array has a read port, a write port and a bidirectional input/output port. The tri-port memory array communicates internally with the supplemental memory array via the bidirectional input/output port and communicates with external devices (e.g., peripheral devices) via the read and write data ports. Efficient steering circuitry is also provided by a bidirectional crosspoint switch that electrically couples terminals (lines IO and IOB) of the bidirectional input/output port in parallel to bit lines (BL and BLB) in the supplemental memory array during a write-to-memory time interval and vice versa during a read-from-memory time interval.
U.S. Pat. Nos. 6,240,031, 6,377,071 and 6,400,642, which are related and commonly assigned to Cypress Semiconductor Corp., disclose a pair of FIFOs that are configured to operate internally in a ping-pong fashion during read and write cycles. Each FIFO in the pair operates at half the frequency of an external clock in order to provide DDR read functions and DDR write functions. U.S. Pat. No. 6,134,180 to Kim et al. discloses a synchronous random access memory (RAM) device that supports burst write operations and burst read operations at single and dual data rates. However, unlike a FIFO memory device, the RAM device disclosed in the '180 patent does not support write and read operations to and from a memory core during overlapping time intervals. FIFO memory devices that support all four combinations of dual data rate (DDR) and single data rate (SDR) write and read operations are disclosed in commonly assigned published U.S. Patent Application No. 2003/0112685.
Notwithstanding the above described memory devices, there still exists a need to develop FIFO memory devices having expanded functionality and increased data capacity. There also exists a need for FIFO memory devices that provide faster data transfer for such applications as network, video, telecommunications and data communications.